IBM and Samsung claim to have made a breakthrough in semiconductor design. On the first day of the IEDM conference in San Francisco, the two companies unveiled a new design for vertical stacking transistors on a chip. In current processors and SoCs, transistors lie flat on the surface of silicon, and then electric current flows from one side to the other. In contrast, vertical field effect transistors (VTFETs) sit perpendicular to each other and current flows vertically.
According to IBM and Samsung, this design has two advantages. First, it will allow them to circumvent many performance limitations to extend Moore’s Law beyond the 1 nanometer threshold. More importantly, the design leads to less energy lost thanks to higher power flow. They estimate that VTFET will lead to processors that are twice as fast and use 85 percent less power than chips designed with FinFET transistors. IBM and Samsung argue that the one-day process could allow phones to run all week with a single charge. They say it could also make certain energy-intensive tasks, including cryptomining, more energy efficient and therefore less environmentally friendly.
IBM and Samsung have not said when they plan to commercialize the design. They are not the only companies trying to cross the 1-nanometer barrier. , Intel said it aims to complete the design for angstrom-sized chips by 2024. The company plans to achieve that feat using its new “Intel 20A” node and RibbonFET transistors.
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